Conventionally, there has been widely used a wiring board having pads arranged in a so-called plurality of rows for a narrow-pitch mounting.
In view of a demand for further reduction in size and weight of electronic devices including the wiring board, electronic components in each of such electronic devices are mounted at a higher density. Accordingly, the wiring board on which the electronic components are mounted are required to have a narrower pitch.
(Patent Literature 1)
In order to meet such a demand, various techniques have been suggested. Patent Literature 1, for example, discloses a technique to arrange a wiring board having pads provided in a plurality of rows. In the technique, the pads are provided in a layer different from a layer in which metal wires each extending between pads adjacent to each other are provided, and the pads have a dual structure. This is described below with reference to FIGS. 15 and 16. FIG. 15 is a view illustrating a configuration of the wiring board disclosed in Patent Literature 1. FIG. 16 is a cross-sectional view taken along line H-H of FIG. 15. The legends “FIRST ROW” and “SECOND ROW” in FIG. 15 indicate respective names of the plurality of rows of pads 105.
The wiring board 100 disclosed in Patent Literature 1, as illustrated in FIG. 15, is provided with metal wires 101 each provided so as to extend between pads 105 in the second row and so as to be connected to a corresponding pad 105 in the first row among all pads 105 arranged in the plurality of rows. The metal wire 101 is provided, as illustrated in FIG. 16, in a layer different from a layer in which the pads 105 in the second row are provided. More specifically, each pad 105 is provided in a layer above the metal wires 101 via an interlayer insulating layer 102 and which is thus different from the layer in which the metal wires 101 are provided.
Each pad 105 in the first and second rows is connected, via a through hole 103, to a corresponding metal wire 101 provided in the layer different from the layer in which the pad 105 is provided (see FIG. 15). Further, a pad 109 having an area larger than that of the pad 105 is provided, via an interlayer insulating layer 106, in a layer above the layer in which the pad 105 is provided. The pad 105 is connected to the pad 109 via a pad through hole 107 (see FIG. 15). In other words, the metal wire 101, the pad 105, and the pad 109 are formed in different layers, respectively. In other words, the metal wire 101 is formed in a first layer; the pad 105 is formed in a second layer; and the pad 109 is formed a third layer.
As described above, according to the wiring board 100 disclosed in Patent Literature 1, the metal wire 101 provided between second-row pads 105 is provided in the layer different from the respective layers of the pad 105 and the pad 109 (the interlayer insulating layer 102 is provided in a layer above the metal wire 101). This makes it possible to reduce a distance between adjacent second-row pads 109 to some extent.
(Patent Literature 2)
With reference to Patent Literature 2, the following describes an example case in which a wiring board on which electronic components are mounted is used as a display device substrate (a substrate for a display device).
Patent Literature 2 discloses a configuration in which pads are arranged on a liquid crystal panel in a plurality of rows in the same manner as in Patent Literature 1. The following description refers to FIGS. 23 to 25. FIG. 23 is a view illustrating a configuration of the liquid crystal panel disclosed in Patent Literature 2. FIG. 24 is a view illustrating a configuration of a bottom surface of a driving integrated circuit (IC) illustrated in FIG. 23. FIG. 25 is a view illustrating the liquid crystal panel on which the driving IC illustrated in FIG. 24 is mounted.
As illustrated in FIG. 23, the liquid crystal panel 300 disclosed in Patent Literature 2 has a driving IC 400 mounted directly thereon (chip on glass (COG) mounting). As illustrated in FIG. 24, the driving IC 400 that is COG-mounted on the liquid crystal panel 300 has a bottom surface having bumps 410 arranged in a plurality of rows. Further, as illustrated in FIG. 25, the liquid crystal panel 300 has a region in which the driving IC 400 is to be mounted. This region has electrode pads 320 that are formed therein so as to correspond to the respective bumps 410 formed on the bottom surface of the driving IC 400. Each of the electrode pads 320 is connected to an input line 310 which is a line connected to a pad.
Citation List
Patent Literature 1
Japanese Patent Application Publication, Tokukaihei, No. 5-29377 A (Publication Date: Feb. 5, 1993)
Patent Literature 2
Japanese Patent Application Publication, Tokukai, No. 2004-252466 A (Publication Date: Sep. 9, 2004)